The present invention relates to a circuit simulation technology for extracting a resistance value and a capacitance value from layout data of a semiconductor integrated circuit and analyzing a noise transmitted through a semiconductor substrate.
Patent Document 1 discloses a simulation method and a device for precisely extracting parasitic elements resulting from a well region and a conductive region of a substrate and performing a circuit simulation. According to the above method and device, the well region is divided into meshes and is modeled using a two-dimensional parasitic resistance and capacitance network.
Patent Document 2 discloses an analyzing device for a semiconductor integrated circuit which performs circuit simulation including influences of parasitic elements in the semiconductor integrated circuit and a method for analyzing a substrate noise. According to the above device and method, behavior of a circuit element is modeled by using a three-dimensional mesh, access ports (well contacts) are simplified, and a load on the circuit simulation is reduced by forming a rough mesh.
Patent Document 3 relates to a noise coupling analysis in a mixed signal system. In particular, it discloses a method and a device for determining a noise in the mixed signal system. In Patent Document 3, “FIG. 2 SPICE substrate model” shows an equivalent circuit having a low-resistance substrate and a twin well configuration.
Patent Document 4 discloses a power MOSFET device formed in the low-resistance substrate.    [Patent Document 1]    Japanese Unexamined Patent Application Publication No. Hei 10(1998)-50849    [Patent Document 2]    Japanese Unexamined Patent Application Publication No. 2002-158284    [Patent Document 3]    United States Patent Application Publication No. 2002/0022951    [Patent Document 4]    Japanese Unexamined Patent Application Publication No. 2003-152180